MC9S12GRMV1 Datasheet, PDF (336/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
8.4.3.3 Immediate Trigger
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of
the current state of ARM.
8.4.3.4 Channel Priorities
In case of simultaneous matches the priority is resolved according to Table 8-36. The lower priority is
suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher
priority. The priorities described in Table 8-36 dictate that in the case of simultaneous matches, the match
pointing to final state has highest priority followed by the lower channel number (0,1,2).
Table 8-36. Channel Priorities
Priority
Highest
Lowest
Source
TRIG
Channel pointing to Final State
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Action
Enter Final State
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
8.4.4 State Sequence Control
ARM = 0
State 0
(Disarmed)
ARM = 1
ARM = 0
State1
State2
ARM = 0
Session Complete
(Disarm)
Final State
State3
Figure 8-24. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
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