MC9S12GRMV1 Datasheet, PDF (380/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.8 S12CPMU RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
0x003B
R
W
Reset
7
RTDEC
0
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
1
RTR1
0
0
0
0
0
0
Figure 10-11. S12CPMU RTI Control Register (CPMURTI)
Read: Anytime
Write: Anytime
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
0
RTR0
0
Table 10-9. CPMURTI Field Descriptions
Field
7
RTDEC
6–4
RTR[6:4]
3–0
RTR[3:0]
Description
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 10-10
1 Decimal based divider value. See Table 10-11
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Table 10-10 and Table 10-11.
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 10-10 and Table 10-11 show all possible divide values selectable by the
CPMURTI register.
MC9S12G Family Reference Manual, Rev.1.23
382
Freescale Semiconductor