MC9S12GRMV1 Datasheet, PDF (232/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.41
Reserved Registers
NOTE
Addresses 0x0260-0x0261 are reserved for ACMP registers in G2 and G3
only. Refer to ACMP section “ACMP Control Register (ACMPC)” and
“ACMP Status Register (ACMPS)”.
2.4.3.42 Port J Data Register (PTJ)
Address 0x0268 (G1, G2)
7
R
PTJ7
W
Reset
0
Address 0x0268 (G3)
6
PTJ6
0
5
PTJ5
0
4
PTJ4
0
3
PTJ3
0
2
PTJ2
0
7
6
5
4
3
2
R
0
0
0
0
PTJ3
PTJ2
W
Reset
0
0
0
0
0
0
Figure 2-42. Port J Data Register (PTJ)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PTJ1
PTJ0
0
0
Access: User read/write¹
1
0
PTJ1
PTJ0
0
0
Field
7-0
PTJ
Table 2-68. PTJ Register Field Descriptions
Description
Port J general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
MC9S12G Family Reference Manual, Rev.1.23
234
Freescale Semiconductor