MC9S12GRMV1 Datasheet, PDF (203/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.1 Port A Data Register (PORTA)
Address 0x0000 (G1)
7
6
5
4
3
2
R
PA7
PA6
PA5
PA4
PA3
PA2
W
Reset
0
0
0
0
0
0
Address 0x0000 (G2, G3)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Figure 2-2. Port A Data Register (PORTA)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PA1
PA0
0
0
Access: User read only
1
0
0
0
0
0
Field
7-0
PA
Table 2-22. PORTA Register Field Descriptions
Description
Port A general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
2.4.3.2 Port B Data Register (PORTB)
Address 0x0001 (G1)
7
6
R
PB7
PB6
W
Reset
0
0
Address 0x0001 (G2, G3)
7
6
R
0
0
W
Reset
0
0
5
PB5
4
PB4
3
PB3
2
PB2
0
0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
Figure 2-3. Port B Data Register (PORTB)
Access: User read/write¹
1
0
PB1
PB0
0
0
Access: User read only
1
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
205