MC9S12GRMV1 Datasheet, PDF (240/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-80. DDR1AD Register Field Descriptions
Field
Description
7-0 Port AD data direction—
DDR1AD This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.55
Reserved Register
NOTE
Address 0x0276 is reserved for RVA on G(A)240 and G(A)192 only. Refer
to RVA section “RVA Control Register (RVACTL)”.
2.4.3.56
Pin Routing Register 1 (PRR1)
NOTE
Routing takes only effect if PKGCR is set to select the 100 LQFP package.
Address 0x0277 (G(A)240 and G(A)192 only)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Address 0x0277 (non G(A)240 and G(A)192)
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-55. Pin Routing Register (PRR1)
Access: User read/write¹
1
0
0
PRR1AN
0
0
Access: User read/write
1
0
0
0
0
0
Table 2-81. PRR1 Register Field Descriptions
Field
Description
0
PRR1AN
Pin Routing Register ADC channels — Select alternative routing for AN15/14/13/11/10 pins to port C
This bit programs the routing of the specific ADC channels to alternative external pins in 100 LQFP. See Table 2-82.
The routing affects the analog signals and digital input trigger paths to the ADC. Refer to the related pin descriptions
in Section 2.3.4, “Pins PC7-0” and Section 2.3.12, “Pins AD15-0”.
1 AN inputs on port C
0 AN inputs on port AD
MC9S12G Family Reference Manual, Rev.1.23
242
Freescale Semiconductor