MC9S12GRMV1 Datasheet, PDF (735/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B6CV3)
1 _{The register is available only if corresponding channel exists.}
22.3.2.1 Timer Input Capture/Output Compare Select (TIOS)
Module Base + 0x0000
7
6
R
RESERVED RESERVED
W
5
IOS5
4
IOS4
3
IOS3
2
IOS2
1
IOS1
Reset
0
0
0
0
0
0
0
Figure 22-4. Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
Table 22-2. TIOS Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
5:0
IOS[5:0]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding implemented channel acts as an input capture.
1 The corresponding implemented channel acts as an output compare.
0
IOS0
0
22.3.2.2 Timer Compare Force Register (CFORC)
Module Base + 0x0001
7
6
5
4
3
2
R
0
0
0
0
0
0
W RESERVED RESERVED FOC5
FOC4
FOC3
FOC2
Reset
0
0
0
0
0
0
Figure 22-5. Timer Compare Force Register (CFORC)
1
0
FOC1
0
0
0
FOC0
0
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 22-3. CFORC Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
Description
5:0
FOC[5:0]
Note: Force Output Compare Action for Channel 5:0 — A write to this register with the corresponding data
bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
737