MC9S12GRMV1 Datasheet, PDF (378/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-5. CPMUCLKS Descriptions (continued)
Field
Description
1
RTI Clock Select — RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
0
COP
OSCSEL0
COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
(see also Table 10-6)
If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK.
Changing the COPOSCSEL0 bit re-starts the COP time-out period.
COPOSCSEL0 can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL0 bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
Table 10-6. COPOSCSEL1, COPOSCSEL0 clock source select description
COPOSCSEL1
0
0
1
COPOSCSEL0
0
1
x
COP clock source
IRCCLK
OSCCLK
ACLK
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor