MC9S12GRMV1 Datasheet, PDF (271/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12G Memory Map Controller (S12GMMCV1)
5.3.2.4 Program Page Index Register (PPAGE)
Address: 0x0015
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PIX3
PIX2
0
0
0
1
1
Figure 5-8. Program Page Index Register (PPAGE)
1
PIX1
1
0
PIX0
0
Read: Anytime
Write: Anytime
The four index bits of the PPAGE register select a 16K page in the global memory map (Figure 5-11). The
selected 16K page is mapped into the paging window ranging from local address 0x8000 to 0xBFFF.
Figure 5-9 illustrates the translation from local to global addresses for accesses to the paging window. The
CPU has special access to read and write this register directly during execution of CALL and RTC
instructions.
Global Address [17:0]
Bit17
Bit14 Bit13
Bit0
PPAGE Register [3:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 5-9. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Table 5-7. PPAGE Field Descriptions
Field
3–0
PIX[3:0]
Description
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 flash array pages
is to be accessed in the Program Page Window.
The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by
Registers, EEPROM and RAM space. See SoC Guide for details.
The fixed 16KB page from 0x4000–0x7FFF is the page number 0xD.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
273