MC9S12GRMV1 Datasheet, PDF (368/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve
the quality of this supply.
NOTE
Depending on the device package following device supply pins are maybe
combined into one pin: VDDR, VDDX and VDDA.
Depending on the device package following device supply pins are maybe
combined into one pin: VSS, VSSX and VSSA.
Please refer to the device Reference Manual for information if device supply
pins are combined into one supply pin for certain packages and which
supply pins are combined together.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between
the combined supply pin pair can improve the quality of this supply.
10.2.7 VDD — Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the core logic.
This supply domain is monitored by the Low Voltage Reset circuit.
10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit
10.2.9 API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
MC9S12G Family Reference Manual, Rev.1.23
370
Freescale Semiconductor