MC9S12GRMV1 Datasheet, PDF (323/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
SC[3:0]
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 8-18. State2 —Sequencer Next State Selection
Description (Unspecified matches have no effect)
Match2 to Final State
Match2 to State1..... Match0 to Final State
Either Match0 or Match1 to Final State
Reserved
Reserved
Reserved
Reserved
Either Match0 or Match1 to Final State........Match2 to State3
Reserved
Reserved
Either Match0 or Match1 to Final State........Match2 to State1
The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.3 Debug State Control Register 3 (DBGSCR3)
Address: 0x0027
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
SC3
SC2
SC1
SC0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
Table 8-19. DBGSCR3 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State3, based upon the match event.
SC[3:0]
0000
Table 8-20. State3 — Sequencer Next State Selection
Description (Unspecified matches have no effect)
Match0 to State1
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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