MC9S12GRMV1 Datasheet, PDF (221/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

PRR0T21
0
0
1
1
PRR0S1
0
0
1
1
Port Integration Module (S12GPIMV1)
Table 2-50. IOC2 Routing Options
PRR0T20
0
1
0
1
IOC2 Associated Pin
PS5 - IOC2
PE0 - IOC2
PAD4 - IOC2
Reserved
Table 2-51. SCI0 Routing Options
PRR0S0
0
1
0
1
SCI0 Associated Pin
PE0 - RXD, PE1 - TXD
PS4 - RXD, PS7 - TXD
PAD4 - RXD, PAD5 - TXD
Reserved
2.4.3.27 Port M Data Register (PTM)
Address 0x0250 (G1, G2)
7
6
5
4
3
2
R
0
0
0
0
PTM3
PTM2
W
Reset
0
0
0
0
0
0
Address 0x0250 (G3)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Figure 2-28. Port M Data Register (PTM)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PTM1
PTM0
0
0
Access: User read/write¹
1
0
PTM1
PTM0
0
0
Field
3-0
PTM
Table 2-52. PTM Register Field Descriptions
Description
Port M general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
223