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| MC9S12GRMV1 Datasheet, PDF (1080/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet | |||
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128 KByte Flash Module (S12FTMRG128K1V1)
29.4.7 Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
Table 29-66. Flash Interrupt Sources
Interrupt Source
Flash Command Complete
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Interrupt Flag
CCIF
(FSTAT register)
DFDIF
(FERSTAT register)
SFDIF
(FERSTAT register)
Local Enable
CCIE
(FCNFG register)
DFDIE
(FERCNFG register)
SFDIE
(FERCNFG register)
Global (CCR)
Mask
I Bit
I Bit
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
29.4.7.1 Description of Flash Interrupt Operation
The Flash module uses the CCIF ï¬ag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF ï¬ags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to Section 29.3.2.5, âFlash Configuration Register
(FCNFG)â, Section 29.3.2.6, âFlash Error Configuration Register (FERCNFG)â, Section 29.3.2.7, âFlash
Status Register (FSTAT)â, and Section 29.3.2.8, âFlash Error Status Register (FERSTAT)â.
The logic used for generating the Flash module interrupts is shown in Figure 29-27.
CCIE
CCIF
Flash Command Interrupt Request
DFDIE
DFDIF
SFDIE
SFDIF
Flash Error Interrupt Request
Figure 29-27. Flash Module Interrupts Implementation
1082
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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