MC9S12GRMV1 Datasheet, PDF (347/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

8.5.3 Scenario 2
A trigger is generated if a given sequence of 2 code events is executed.
Figure 8-28. Scenario 2a
SCR1=0011
SCR2=0101
State1
M1
State2
M2
Final State
S12S Debug Module (S12SDBGV2)
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
Figure 8-29. Scenario 2b
SCR1=0111
SCR2=0101
State1
M01 _State2
M2
Final State
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
Figure 8-30. Scenario 2c
SCR1=0010
SCR2=0011
State1
M2
State2
M0
Final State
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
8.5.4 Scenario 3
A trigger is generated immediately when one of up to 3 given events occurs
Figure 8-31. Scenario 3
SCR1=0000
State1
M012 _{Final State}
Scenario 3 is possible with S12SDBGV1 SCR encoding
8.5.5 Scenario 4
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
MC9S12G Family Reference Manual, Rev.1.23
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