MC9S12GRMV1 Datasheet, PDF (217/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Field
7-0
PTS
Table 2-40. PTS Register Field Descriptions
Description
Port S general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
2.4.3.21 Port S Input Register (PTIS)
Address 0x0249
R
W
Reset
7
PTIS7
0
1 _{Read: Anytime}
Write:Never
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
0
0
0
0
0
Figure 2-22. Port S Input Register (PTIS)
Access: User read only¹
1
PTIS1
0
PTIS0
0
0
Field
7-0
PTIS
Table 2-41. PTIS Register Field Descriptions
Description
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.22 Port S Data Direction Register (DDRS)
Address 0x024A
R
W
Reset
7
DDRS7
0
1 _{Read: Anytime}
Write: Anytime
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 2-23. Port S Data Direction Register (DDRS)
Access: User read/write¹
1
0
DDRS1
DDRS0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
219