MC9S12GRMV1 Datasheet, PDF (376/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)
This register controls S12CPMU clock selection.
0x0039
R
W
Reset
7
PLLSEL
1
6
PSTP
5
4
3
0
COP
OSCSEL1
PRE
2
PCE
1
RTI
OSCSEL
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS)
0
COP
OSCSEL0
0
Read: Anytime
Write:
1. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
2. All bits in Special Mode (if PROT=0).
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
4. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1
or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
5. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once is taken.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with
COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for
other clock domains: for instance core clock etc.).
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful.
MC9S12G Family Reference Manual, Rev.1.23
378
Freescale Semiconductor