MC9S12GRMV1 Datasheet, PDF (379/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.7 S12CPMU PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
0x003A
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
FM1
FM0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-10. S12CPMU PLL Control Register (CPMUPLL)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Table 10-7. CPMUPLL Field Descriptions
Field
Description
5, 4
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
FM1, FM0 is to reduce noise emission. The modulation frequency is f_ref divided by 16. See Table 10-8 for coding.
Table 10-8. FM Amplitude selection
FM1
0
0
1
1
FM0
0
1
0
1
FM Amplitude /
f_VCO Variation
FM off
±1%
±2%
±4%
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
381