MC9S12GRMV1 Datasheet, PDF (815/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

16 KByte Flash Module (S12FTMRG16K1V1)
24.4.6.11 Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 24-10). The Verify Backdoor Access Key command releases security if
user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see
Table 24-4). The Verify Backdoor Access Key command must not be executed from the Flash block
containing the backdoor comparison key to avoid code runaway.
Table 24-50. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
001
010
011
100
FCCOB Parameters
0x0C
Key 0
Key 1
Key 2
Key 3
Not required
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
Table 24-51. Verify Backdoor Access Key Command Error Handling
Register
FSTAT
Error Bit
ACCERR
FPVIOL
MGSTAT1
MGSTAT0
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 24.3.2.2)
Set if the backdoor key has mismatched since the last reset
None
None
None
24.4.6.12 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of the P-Flash or EEPROM block.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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