MC9S12GRMV1 Datasheet, PDF (168/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
This section describes the signals available on each pin.
Although trying to enable multiple signals on a shared pin is not a proper use case in most applications,
the resulting pin function will be determined by a predefined priority scheme as defined in 2.2.2 and 2.2.3.
Only enabled signals arbitrate for the pin and the highest priority defines its data direction and output value
if used as output. Signals with programmable routing options are assumed to select the appropriate target
pin to participate in the arbitration.
The priority is represented for each pin with shared signals from highest to lowest in the following format:
SignalA > SignalB > GPO
Here SignalA has priority over SignalB and general-purpose output function (GPO; represented by related
port data register bit). The general-purpose output is always of lowest priority if no other signal is enabled.
Peripheral input signals on shared pins are always connected monitoring the pin level independent of their
use.
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor