MC9S12GRMV1 Datasheet, PDF (559/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

SMP2
1
Analog-to-Digital Converter (ADC12B16CV2)
Table 16-13. Sample Time Select
SMP1
1
SMP0
1
Sample Time
in Number of
ATD Clock Cycles
24
16.3.2.6 ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If the
external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting
of a conversion sequence which will then occur on each trigger event. Start of conversion means the
beginning of the sampling phase.
Module Base + 0x0005
7
R
0
W
6
5
4
3
2
1
0
SC
SCAN
MULT
CD
CC
CB
CA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
Table 16-14. ATDCTL5 Field Descriptions
Field
6
SC
5
SCAN
Description
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5. Table 16-15 lists the coding.
0 Special channel conversions disabled
1 Special channel conversions enabled
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect,
thus the external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
561