MC9S12GRMV1 Datasheet, PDF (266/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12G Memory Map Controller (S12GMMCV1)
5.1.3 Features
The main features of this block are:
• Paging capability to support a global 256 KByte memory address space
• Bus arbitration between the masters CPU12, S12SBDM to different resources.
• MCU operation mode control
• MCU security control
• Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address
which does not belong to any of the on-chip modules) in single-chip modes
5.1.4 Modes of Operation
The S12GMMC selects the MCU’s functional mode. It also determines the devices behavior in secured
and unsecured state.
5.1.4.1 Functional Modes
Two functional modes are implemented on devices of the S12G product family:
• Normal Single Chip (NS)
The mode used for running applications.
• Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals
may also provide special debug features in this mode.
5.1.4.2 Security
S12G devices can be secured to prohibit external access to the on-chip flash. The S12GMMC module
determines the access permissions to the on-chip memories in secured and unsecured state.
5.1.5 Block Diagram
Figure 5-1 shows a block diagram of the S12GMMC.
MC9S12G Family Reference Manual, Rev.1.23
268
Freescale Semiconductor