MC9S12GRMV1 Datasheet, PDF (158/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-3. Port Pin Availability (in largest package) per Device
Device Group
Port
G1
G2
G3
(100 pin)
(64 pin)
(48 pin)
C
7-0
-
-
D
7-0
-
-
E
1-0
1-0
1-0
T
7-0
7-0
5-0
S
7-0
7-0
7-0
M
3-0
3-0
1-0
P
7-0
7-0
5-0
J
7-0
7-0
3-0
AD
15-0
15-0
11-0
2.2.1 Package Code
The availability of pins and the related peripheral signals are determined by a package code
(Section 2.4.3.33, “Package Code Register (PKGCR)”). The related value is loaded from a factory
programmed non-volatile memory location into the register during the reset sequence.
Based on the package code all non-bonded pins will have the input buffer disabled to avoid shoot-through
current resulting in excess current in stop mode.
2.2.2 Prioritization
If more than one output signal is attempted to be enabled on a specific pin, a priority scheme determines
the signal taking effect.
General rules:
• The peripheral with the highest amount of pins has priority on the related pins when it is enabled.
• If a peripheral can selectively disable a function, the freed up pin is used with the next enabled
peripheral signal.
• The general-purpose output function takes control if no peripheral function is enabled.
Input signals are not prioritized. Therefore the input function remains active (for example timer input
capture) even if a pin is used with the output signal of another peripheral or general-purpose output.
2.2.3 Signals and Priorities
Table 2-4 shows all pins with their related signals per device and package that are controlled by the PIM.
A signal name in squared brackets denotes the port register bit related to the digital I/O function of the pin
(port register PORT/PT not listed). It is a representative for any other port related register bit with the same
MC9S12G Family Reference Manual, Rev.1.23
160
Freescale Semiconductor