MC9S12GRMV1 Datasheet, PDF (186/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-18. Block Memory Map (0x0000-0x027F) (continued)
Port
Global
Address
Register
0x0260 Reserved for ACMP available in group G2 and G3
0x0261
0x0262
:
0x0266
Reserved
J
0x0268 PTJ—Port J Data Register
0x0269 PTIJ—Port J Input Register
0x026A DDRJ—Port J Data Direction Register
0x026B Reserved
0x026C PERJ—Port J Pull Device Enable Register
0x026D PPSJ—Port J Polarity Select Register
0x026E PIEJ—Port J Interrupt Enable Register
0x026F PIFJ—Port J Interrupt Flag Register
AD 0x0270 PT0AD—Port AD Data Register
0x0271 PT1AD—Port AD Data Register
0x0272 PTI0AD—Port AD Input Register
0x0273 PTI1AD—Port AD Input Register
0x0274 DDR0AD—Port AD Data Direction Register
0x0275 DDR1AD—Port AD Data Direction Register
0x0276
0x0277
Reserved for RVACTL on G(A)240 and G(A)192 only
PRR1—Pin Routing Register 1⁶
0x0278 PER0AD—Port AD Pull Device Enable Register
0x0279 PER1AD—Port AD Pull Device Enable Register
0x027A PPS0AD—Port AD Polarity Select Register
0x027B PPS1AD—Port AD Polarity Select Register
0x027C PIE0AD—Port AD Interrupt Enable Register
0x027D PIE1AD—Port AD Interrupt Enable Register
0x027E PIF0AD—Port AD Interrupt Flag Register
0x027F PIF1AD—Port AD Interrupt Flag Register
1 _{Available in group G1 only. In any other case this address is reserved.}
2 _{Refer to device memory map to determine related module.}
3 _{Read always returns logic level on pins.}
4 _{Routing takes only effect if the PKGCR is set to 20 TSSOP.}
Access Reset Value
R(/W)
R(/W)
R
0x00
0x00
0x00
Section/Page
(ACMP)
(ACMP)
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R(/W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
3
0x00
0x00
0xFF (G1,G2)
0x0F (G3)
0x00
0x00
0x00
0x00
0x00
3
3
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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(RVA)
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MC9S12G Family Reference Manual, Rev.1.23
188
Freescale Semiconductor