MC9S12GRMV1 Datasheet, PDF (409/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid.
2. Enable the external oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
• PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
• The OSCCLK provided to the MSCAN module is off.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
10.5 Resets
10.5.1 General
All reset sources are listed in Table 10-26. Refer to MCU specification for related vector addresses and
priorities.
Table 10-26. Reset Summary
Reset Source
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock Monitor Reset
COP Reset
Local Enable
None
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
10.5.2 Description of Reset Operation
Upon detection of any reset of Table 10-26, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 10-27 shows which vector will be fetched.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
411