MC9S12GRMV1 Datasheet, PDF (369/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1 Module Memory Map
The S12CPMU registers are shown in Figure 10-3.
Addres
s
Name
0x0034
CPMU
SYNR
R
W
0x0035
CPMU
REFDIV
R
W
0x0036
CPMU
POSTDIV
R
W
R
0x0037 CPMUFLG
W
R
0x0038 CPMUINT
W
R
0x0039 CPMUCLKS
W
R
0x003A CPMUPLL
W
R
0x003B CPMURTI
W
R
0x003C CPMUCOP
W
0x003D
RESERVEDCP
MUTEST0
R
W
0x003E
RESERVEDCP
MUTEST1
R
W
0x003F
CPMU
ARMCOP
R
W
R
0x02F0 RESERVED
W
0x02F1
CPMU
LVCTL
R
W
0x02F2
CPMU
APICTL
R
W
Bit 7
6
5
4
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
0
RTIF
RTIE
PORF
0
PLLSEL
0
PSTP
0
LVRF
0
0
LOCKIF
LOCKIE
COP
OSCSEL1
FM1
FM0
RTDEC
WCOP
0
RTR6
RTR5
RTR4
0
0
RSBCK
WRTMASK
0
0
0
0
0
0
0
0
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
0
0
0
0
APICLK
0
APIES
= Unimplemented or Reserved
3
2
1
SYNDIV[5:0]
REFDIV[3:0]
POSTDIV[4:0]
LOCK
ILAF
OSCIF
0
0
OSCIE
PRE
0
PCE
0
RTI
OSCSEL
0
RTR3
0
0
RTR2
CR2
0
0
0
0
Bit 3
0
0
Bit 2
0
0
LVDS
APIEA APIFE
RTR1
CR1
0
0
0
Bit 1
0
LVIE
APIE
Bit 0
UPOSC
0
COP
OSCSEL0
0
RTR0
CR0
0
0
0
Bit 0
0
LVIF
APIF
Figure 10-3. CPMU Register Summary
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
371