MC9S12GRMV1 Datasheet, PDF (325/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
Table 8-21. Comparator Register Layout
CONTROL
ADDRESS HIGH
ADDRESS MEDIUM
ADDRESS LOW
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
DATA HIGH MASK
DATA LOW MASK
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparator A only
Comparator A only
Comparator A only
Comparator A only
8.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Address: 0x0028
R
W
Reset
7
SZE
0
6
5
4
3
2
1
SZ
TAG
BRK
RW
RWE
NDB
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)
0
COMPE
0
Address: 0x0028
7
6
5
4
3
2
1
R
0
SZE
SZ
TAG
BRK
RW
RWE
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B)
0
COMPE
0
Address: 0x0028
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
TAG
BRK
RW
RWE
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C)
0
COMPE
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
327