MC9S12GRMV1 Datasheet, PDF (742/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B6CV3)
Table 22-13. TRLG1 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
5:0
C[5:0]F
Description
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
22.3.2.11 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 22-17. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 .
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 22-14. TRLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one (See also TCRE control
bit explanation.)
MC9S12G Family Reference Manual, Rev.1.23
744
Freescale Semiconductor