MC9S12GRMV1 Datasheet, PDF (733/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

IOCn
Edge detector
16-bit Main Timer
TCn Input Capture Reg.
Timer Module (TIM16B6CV3)
Set CnF Interrupt
Figure 22-2. Interrupt Flag Setting
22.2 External Signal Description
The TIM16B6CV3 module has a selected number of external pins. Refer to device specification for exact
number.
22.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0
Those pins serve as input capture or output compare for TIM16B6CV3 channel .
NOTE
For the description of interrupts see Section 22.6, “Interrupts”.
22.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
22.3.1 Module Memory Map
The memory map for the TIM16B6CV3 module is given below in Figure 22-3. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B6CV3 module and the address offset for each register.
22.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
735