MC9S12GRMV1 Datasheet, PDF (392/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
0x02F4
R
W
Reset
7
APIR15
6
APIR14
5
APIR13
4
APIR12
3
APIR11
2
APIR10
1
APIR9
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-20. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0
APIR8
0
0x02F5
R
W
Reset
7
APIR7
6
APIR6
5
APIR5
4
APIR4
3
APIR3
2
APIR2
1
APIR1
0
0
0
0
0
0
0
Figure 10-21. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
0
APIR0
0
Read: Anytime
Write: Anytime if APIFE=0. Else writes have no effect.
Table 10-19. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field
Description
15-0
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
APIR[15:0] Table 10-20 for details of the effect of the autonomous periodical interrupt rate bits.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * f_ACLK
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
NOTE
For APICLK bit clear the first time-out period of the API will show a latency
time between two to three f_ACLK cycles due to synchronous clock gate
release when the API feature gets enabled (APIFE bit set).
MC9S12G Family Reference Manual, Rev.1.23
394
Freescale Semiconductor