MC9S12GRMV1 Datasheet, PDF (642/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Pulse-Width Modulator (S12PWM8B8CV2)
Module Base + 0x0001
R
W
Reset
7
PPOL7
0
6
PPOL6
5
PPOL5
4
PPOL4
3
PPOL3
2
PPOL2
0
0
0
0
0
Figure 19-4. PWM Polarity Register (PWMPOL)
1
PPOL1
0
0
PPOL0
0
Read: Anytime
Write: Anytime
NOTE
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
Table 19-3. PWMPOL Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field
Description
7–0
PPOL[7:0]
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
reached.
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
reached.
19.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of four clocks to use as the clock source for that channel as described
below.
Module Base + 0x0002
R
W
Reset
7
PCLK7
0
6
PCLKL6
5
PCLK5
4
PCLK4
3
PCLK3
2
PCLK2
0
0
0
0
0
Figure 19-5. PWM Clock Select Register (PWMCLK)
1
PCLK1
0
0
PCLK0
0
Read: Anytime
Write: Anytime
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
MC9S12G Family Reference Manual, Rev.1.23
644
Freescale Semiconductor