MC9S12GRMV1 Datasheet, PDF (708/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Serial Peripheral Interface (S12SPIV5)
Table 21-1. SPICR1 Field Descriptions
Field
4
MSTR
3
CPOL
2
CPHA
1
SSOE
0
LSBFE
Description
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in Table 21-2. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
MODFEN
0
0
1
1
Table 21-2. SS Input / Output Selection
SSOE
0
1
0
1
Master Mode
SS not used by SPI
SS not used by SPI
SS input with MODF feature
SS is slave select output
Slave Mode
SS input
SS input
SS input
SS input
21.3.2.2 SPI Control Register 2 (SPICR2)
Module Base +0x0001
7
R
0
W
6
XFRW
5
4
3
2
0
0
MODFEN BIDIROE
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-4. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
1
SPISWAI
0
0
SPC0
0
MC9S12G Family Reference Manual, Rev.1.23
710
Freescale Semiconductor