MC9S12GRMV1 Datasheet, PDF(477/1292 Page) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

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MC9S12GRMV1 Datasheet, PDF (477/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

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Analog-to-Digital Converter (ADC10B12CV2)

Table 13-6. ATDCTL2 Field Descriptions

Field

Description

6

AFFC

5

Reserved

4

ETRIGLE

3

ETRIGP

2

ETRIGE

1

ASCIE

0

ACMPIE

ATD Fast Flag Clear All

0 ATD ï¬ag clearing done by write 1 to respective CCF[n] ï¬ag.

1 Changes all ATD conversion complete ï¬ags to a fast clear sequence.

For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ï¬ag

to clear automatically.

For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ï¬ag

to clear automatically.

Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.

External Trigger Level/Edge Control â This bit controls the sensitivity of the external trigger signal. See

Table 13-7 for details.

External Trigger Polarity â This bit controls the polarity of the external trigger signal. See Table 13-7 for details.

External Trigger Mode Enable â This bit enables the external trigger on one of the AD channels or one of the

ETRIG3-0 inputs as described in Table 13-5. If the external trigger source is one of the AD channels, the digital

input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with

external events.

0 Disable external trigger

1 Enable external trigger

ATD Sequence Complete Interrupt Enable

0 ATD Sequence Complete interrupt requests are disabled.

1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.

ATD Compare Interrupt Enable â If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE

register) this bit enables the compare interrupt. If the CCF[n] ï¬ag is set (showing a successful compare for

conversion n), the compare interrupt is triggered.

0 ATD Compare interrupt requests are disabled.

1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare

Interrupt will be requested whenever any of the respective CCF ï¬ags is set.

Table 13-7. External Trigger Conï¬gurations

ETRIGLE

0

0

1

1

ETRIGP

0

1

0

1

External Trigger Sensitivity

Falling edge

Rising edge

Low level

High level

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor

479

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