MC9S12GRMV1 Datasheet, PDF (289/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

7.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 7-1.
Host
System _BKGD
Serial
Interface
Register Block
Data
Control
16-Bit Shift Register
TRACE
BDMACT
Instruction Code
and
Execution
Background Debug Module (S12SBDMV1)
Bus Interface
and
Control Logic
Address
Data
Control
Clocks
ENBDM
SDV
UNSEC
BDMSTS
Register
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
Figure 7-1. BDM Block Diagram
7.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is always the BDM clock frequency defined
at device level (refer to device overview section). When modifying the VCO clock please make sure that
the communication rate is adapted accordingly and a communication time-out (BDM soft reset) has
occurred.
7.3 Memory Map and Register Definition
7.3.1 Module Memory Map
Table 7-2 shows the BDM memory map when BDM is active.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
291