MC9S12GRMV1 Datasheet, PDF (1247/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Detailed Register Address Map
Appendix B
Detailed Register Address Map
Revision History
Version
Number
Revision
Date
Rev 0.05 30-Aug-2010
Rev 0.06
Rev 0.07
Rev 0.08
Rev 0.09
18-Oct-2010
9-Nov-2010
4-Dec-2010
24-Apr-2012
Description of Changes
• Updated ADCCTL2 register in Appendix B, “Detailed Register Address Map”.
• Updated CPMUOSC register in Appendix B, “Detailed Register Address Map”.
• Updated ADC registers in Appendix B, “Detailed Register Address Map”.
• Updated CPMU registers in Appendix B, “Detailed Register Address Map”.
• Updated PIM registers in Appendix B, “Detailed Register Address Map”.
• Typos and formatting
B.1 Detailed Register Map
The following tables show the detailed register map of the MC9S12G-Family.
NOTE
This is a summary of all register bits implemented on MC9S12G devices.
Each member of the MC9S12G-Family implements the subset of registers,
which is associated with its feature set (see Table 1-1).
0x0000–0x0009 Port Integration Module (PIM) Map 1 of 6
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Name
PORTA
PORTB
DDRA
DDRB
PORTC
PORTD
DDRC
DDRD
PORTE
DDRE
Bit 7
R
PA7
W
R
PB7
W
R
DDRA7
W
R
DDRB7
W
R
PC7
W
R
PD7
W
R
DDRC7
W
R
DDRD7
W
R
0
W
R
0
W
Bit 6
PA6
PB6
DDRA6
DDRB6
PC6
PD6
DDRC6
DDRD6
0
0
Bit 5
PA5
PB5
DDRA5
DDRB5
PC5
PD5
DDRC5
DDRD5
0
0
Bit 4
PA4
PB4
DDRA4
DDRB4
PC4
PD4
DDRC4
DDRD4
0
0
Bit 3
PA3
PB3
DDRA3
DDRB3
PC3
PD3
DDRC3
DDRD3
0
0
Bit 2
PA2
PB2
DDRA2
DDRB2
PC2
PD2
DDRC2
DDRD2
0
0
Bit 1
PA1
PB1
DDRA1
DDRB1
PC1
PD1
DDRC1
DDRD1
PE1
DDRE1
Bit 0
PA 0
PB0
DDRA0
DDRB0
PC0
PD0
DDRC0
DDRD0
PE0
DDRE0
Freescale Semiconductor
MC9S12G Family Reference Manual, Rev.1.23
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