MC9S12GRMV1 Datasheet, PDF (238/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-76. PT1AD Register Field Descriptions
Field
Description
7-0
PT1AD
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”).
2.4.3.51 Port AD Input Register (PTI0AD)
Address 0x0272 (G1, G2)
7
R PTI0AD7
W
Reset
0
Address 0x0272 (G3)
6
PTI0AD6
0
5
PTI0AD5
0
4
PTI0AD4
0
3
PTI0AD3
0
2
PTI0AD2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Never
6
5
4
3
2
0
0
0
PTI0AD3 PTI0AD2
0
0
0
0
0
Figure 2-51. Port AD Input Register (PTI0AD)
Access: User read only¹
1
PTI0AD1
0
PTI0AD0
0
0
Access: User read only¹
1
PTI0AD1
0
PTI0AD0
0
0
Table 2-77. PTI0AD Register Field Descriptions
Field
Description
7-0 Port AD input data—
PTI0AD A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.52 Port AD Input Register (PTI1AD)
Address 0x0273
R
W
Reset
7
PTI1AD7
0
1 _{Read: Anytime}
Write: Never
6
PTI1AD6
5
PTI1AD5
4
PTI1AD4
3
PTI1AD3
2
PTI1AD2
0
0
0
0
0
Figure 2-52. Port AD Input Register (PTI1AD)
Access: User read only¹
1
PTI1AD1
0
PTI1AD0
0
0
MC9S12G Family Reference Manual, Rev.1.23
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