MC9S12GRMV1 Datasheet, PDF (1148/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

240 KByte Flash Module (S12FTMRG240K2V1)
Table 31-8. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
MIN¹
MAX²
FDIV[5:0]
BUSCLK Frequency
(MHz)
MIN¹
MAX²
1.0
1.6
0x00
16.6
17.6
1.6
2.6
0x01
17.6
18.6
2.6
3.6
0x02
18.6
19.6
3.6
4.6
0x03
19.6
20.6
4.6
5.6
0x04
20.6
21.6
5.6
6.6
0x05
6.6
7.6
0x06
7.6
8.6
0x07
8.6
9.6
0x08
9.6
10.6
0x09
10.6
11.6
0x0A
11.6
12.6
0x0B
12.6
13.6
0x0C
13.6
14.6
0x0D
21.6
22.6
22.6
23.6
23.6
24.6
24.6
25.6
14.6
15.6
0x0E
15.6
16.6
0x0F
1 _{BUSCLK is Greater Than this value.}
2 _{BUSCLK is Less Than or Equal to this value.}
FDIV[5:0]
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
31.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
6
5
4
3
2
R
KEYEN[1:0]
RNV[5:2]
W
Reset
F¹
F¹
F¹
F¹
F¹
F¹
= Unimplemented or Reserved
Figure 31-6. Flash Security Register (FSEC)
1 _{Loaded from IFR Flash configuration field, during reset sequence.}
1
0
SEC[1:0]
F¹
F¹
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 31-4) as
1150
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor