MC9S12GRMV1 Datasheet, PDF (339/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
MARK1
MARK2
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX
#SUB_1
JMP
0,X
NOP
; IRQ interrupt occurs during execution of this
;
SUB_1
ADDR1
BRN
NOP
DBNE
*
A,PART5
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB
#$F0
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB
VAR_C1
RTI
;
The execution flow taking into account the IRQ is as follows
LDX
#SUB_1
MARK1 JMP
0,X
;
IRQ_ISR LDAB
#$F0
;
STAB
VAR_C1
RTI
;
SUB_1 BRN
*
NOP
;
ADDR1 DBNE
A,PART5
;
8.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
DBG module writes this value into a background register. This prevents consecutive duplicate address
entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG
module is designed to help find.
8.4.5.2.3 Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode is intended to supply additional information on indexed, indirect addressing modes where storing
only the destination address would not provide all information required for a user to determine where the
code is in error. This mode also features information bit storage to the trace buffer, for each address byte
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
341