MC9S12GRMV1 Datasheet, PDF (250/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-92. Pin Configuration Summary
DDR
IO
PE
PS¹
IE²
Function
Pull Device Interrupt
0
x
0
x
0
Input³
0
x
1
0
0
Input³
0
x
1
1
0
Input³
0
x
0
0
1
Input³
0
x
0
1
1
Input³
0
x
1
0
1
Input³
0
x
1
1
1
Input³
Disabled
Pullup
Pulldown
Disabled
Disabled
Pullup
Pulldown
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
1
0
x
x
0
Output, drive to 0
Disabled
Disabled
1
1
x
x
0
Output, drive to 1
Disabled
Disabled
1
0
x
0
1
Output, drive to 0
Disabled
Falling edge
1
1
x
1
1
Output, drive to 1
Disabled
Rising edge
1 _{Always “0” on port A, B, C, D, BKGD. Always “1” on port E}
2 _{Applicable only on port P, J and AD.}
3 _{Port AD: Assuming digital input buffer enabled in ADC module (ATDDIEN) and ACMP module (ACDIEN)}
2.5.4 Interrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses
and interrupt priorities are defined at MCU level.
Table 2-93. PIM Interrupt Sources
Module Interrupt Sources
Local Enable
XIRQ
IRQ
Port P pin interrupt
Port J pin interrupt
Port AD pin interrupt
None
IRQCR[IRQEN]
PIEP[PIEP7-PIEP0]
PIEJ[PIEJ7-PIEJ0]
PIE0AD[PIE0AD7-PIE0AD0]
PIE1AD[PIE1AD7-PIE1AD0]
2.5.4.1 XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit
in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To
enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register.
The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN]
is cleared while an interrupt is pending, the request will deassert.
MC9S12G Family Reference Manual, Rev.1.23
252
Freescale Semiconductor