MC9S12GRMV1 Datasheet, PDF (467/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Chapter 13
Analog-to-Digital Converter (ADC10B12CV2)
Revision History
Version Revision
Number Date
Effective
Date
V02.00 13 May 2009 13 May 2009
V02.01 30.Nov 2009 30.Nov 2009
V02.02 09 Feb 2010 09 Feb 2010
V02.03 26 Feb 2010 26 Feb 2010
V02.04 14 Apr 2010 14 Apr 2010
V02.05 25 Aug 2010 25 Aug 2010
V02.06 09 Sep 2010 09 Sep 2010
V02.07 11 Feb 2011 11 Feb 2011
V02.08 29 Mar 2011 29 Mar 2011
V02.09 22. Jun 2012 22. Jun 2012
V02.10 29 Jun 2012 29. Jun 2012
V02.11 02 Oct 2012 02 Oct 2012
Author
Description of Changes
Initial version copied from V01.06,
changed unused Bits in ATDDIEN to read logic 1
Updated Table 13-15 Analog Input Channel Select Coding -
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section 13.3.2.12.1/13-489 and 13.3.2.12.2/13-490 and
added table Table 13-21 to improve feature description.
Fixed typo in Table 13-9- conversion result for 3mV and 10bit
resolution
Corrected Table 13-15 Analog Input Channel Select Coding -
description of internal channels.
Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
Removed feature of conversion during STOP and general
wording clean up done in Section 13.4, “Functional
Description
Update of internal only information.
Connectivity Information regarding internal channel_6 added
to Table 13-15.
Fixed typo in bit description field Table 13-14 for bits CD, CC,
CB, CA. Last sentence contained a wrong highest channel
number (it is not AN7 to AN0 instead it is AN11 to AN0).
Update of register write access information in section
13.3.2.9/13-487.
Removed IP name in block diagram Figure 13-1
Added user information to avoid maybe false external trigger
events when enabling the external trigger mode
(Section 13.4.2.1, “External Trigger Input).
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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