MC9S12GRMV1 Datasheet, PDF (740/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B6CV3)
Table 22-9. Edge Detector Circuit Configuration
EDGnB
1
EDGnA
1
Configuration
Capture on any edge (rising or falling)
22.3.2.8 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
RESERVED RESERVED
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 22-14. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 22-10. TIE Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field
5:0
C5I:C0I
Description
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
22.3.2.9 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
TOI
RESERVED
PR2
PR1
PR0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-15. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor