MC9S12GRMV1 Datasheet, PDF (640/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Pulse-Width Modulator (S12PWM8B8CV2)
Register
Name
Bit 7
6
5
4
3
2
1
0x0025 R
0
0
0
0
0
0
0
RESERVED _W
0x0026 R
0
0
0
0
0
0
0
RESERVED _W
0x0027 R
0
0
0
0
0
0
0
RESERVED _W
= Unimplemented or Reserved
Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4)
1 _{The related bit is available only if corresponding channel exists.}
2 _{The register is available only if corresponding channel exists.}
Bit 0
0
0
0
19.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts
off for power savings.
Module Base + 0x0000
R
W
Reset
7
PWME7
0
6
PWME6
5
PWME5
4
PWME4
3
PWME3
2
PWME2
0
0
0
0
0
Figure 19-3. PWM Enable Register (PWME)
1
PWME1
0
0
PWME0
0
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.23
642
Freescale Semiconductor