MC9S12GRMV1 Datasheet, PDF (762/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B8CV3)
Write: Anytime.
Table 23-11. TCTL3/TCTL4 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
7:0
EDGnB
EDGnA
Description
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 23-12. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
23.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 23-18. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 23-13. TIE Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field
7:0
C7I:C0I
Description
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
MC9S12G Family Reference Manual, Rev.1.23
764
Freescale Semiconductor