MC9S12GRMV1 Datasheet, PDF (894/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

48 KByte Flash Module (S12FTMRG48K1V1)
Table 26-16. FERSTAT Field Descriptions
Field
Description
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
returning invalid data was attempted on a Flash block that was under a Flash command operation.¹ The DFDIF
flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.²
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
running
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation.¹ The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
while command running
1 _{The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either}
single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data
attempted while command running) is indicated when both SFDIF and DFDIF flags are high.
2 _{There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after}
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
26.3.2.9 P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
Offset Module Base + 0x0008
R
W
Reset
7
FPOPEN
F¹
6
RNV6
F¹
5
FPHDIS
F¹
4
3
FPHS[1:0]
F¹
F¹
2
FPLDIS
F¹
= Unimplemented or Reserved
Figure 26-13. Flash Protection Register (FPROT)
1 _{Loaded from IFR Flash configuration field, during reset sequence.}
1
0
FPLS[1:0]
F¹
F¹
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 26.3.2.9.1, “P-Flash Protection Restrictions,” and Table 26-21).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 26-4)
as indicated by reset condition ‘F’ in Figure 26-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor