MC9S12GRMV1 Datasheet, PDF (552/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Analog-to-Digital Converter (ADC12B16CV2)
16.3.2 Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
16.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
7
6
5
4
R
0
0
0
Reserved
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
WRAP3
1
2
WRAP2
1
Read: Anytime
Figure 16-3. ATD Control Register 0 (ATDCTL0)
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 16-1. ATDCTL0 Field Descriptions
Field
Description
1
WRAP1
1
0
WRAP0
1
3-0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[3-0] multi-channel conversions. The coding is summarized in Table 16-2.
Table 16-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
Reserved¹
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
MC9S12G Family Reference Manual, Rev.1.23
554
Freescale Semiconductor