MC9S12GRMV1 Datasheet, PDF (239/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-78. PTI1AD Register Field Descriptions
Field
Description
7-0 Port AD input data—
PTI1AD A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.53 Port AD Data Direction Register (DDR0AD)
Address 0x0274 (G1, G2)
Access: User read/write¹
7
R
DDR0AD7
W
Reset
0
Address 0x0274 (G3)
6
DDR0AD6
0
5
DDR0AD5
0
4
DDR0AD4
0
3
DDR0AD3
0
2
DDR0AD2
0
1
0
DDR0AD1 DDR0AD0
0
0
Access: User read/write¹
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
1
0
0
0
0
DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0
0
0
0
0
0
0
0
Figure 2-53. Port AD Data Direction Register (DDR0AD)
Table 2-79. DDR0AD Register Field Descriptions
Field
Description
7-0 Port AD data direction—
DDR0AD This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.54 Port AD Data Direction Register (DDR1AD)
Address 0x0275
7
R
DDR1AD7
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2
0
0
0
0
0
Figure 2-54. Port AD Data Direction Register (DDR1AD)
Access: User read/write¹
1
0
DDR1AD1 DDR1AD0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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