MC9S12GRMV1 Datasheet, PDF (173/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

2.3.8
PS7
PS6
PS5
Port Integration Module (S12GPIMV1)
Pins PS7-0
Table 2-12. Port S Pins PS7-0
• The SPI0 SS signal is mapped to this pin when used with the SPI function. Depending on the
configuration of the enabled SPI0 the I/O state is forced to be input or output.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0
TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
• 20 TSSOP: The PWM channel 3 signal is mapped to this pin when used with the PWM function. If the
PWM channel is enabled and routed here the I/O state is forced to output.The enabled PWM channel
forces the I/O state to be an output.
• 32 LQFP: The PWM channel 5 signal is mapped to this pin when used with the PWM function. The
enabled PWM channel forces the I/O state to be an output.
• 64/48/32/20 LQFP: The ECLK signal is mapped to this pin when used with the external clock function.
If the ECLK output is enabled the I/O state will be forced to output.
• The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the
Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.
• 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The
enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External
Triggers ETRIG3-0”.
• Signal priority:
20 TSSOP: SS0 > TXD0 > PWM3 > ECLK > API_EXTCLK > GPO
32 LQFP: SS0 > PWM5 > ECLK > API_EXTCLK > GPO
48/64 LQFP: SS0 > ECLK > API_EXTCLK > GPO
100 LQFP: SS0 > API_EXTCLK > GPO
• The SPI0 SCK signal is mapped to this pin when used with the SPI function. Depending on the
configuration of the enabled SPI0 the I/O state is forced to be input or output.
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. If the
TIM output compare signal is enabled and routed here the I/O state will be forced to output.
• 32 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. If the TIM
output compare signal is enabled and routed here the I/O state will be forced to output. If the ACMP
timer link is enabled this pin is disconnected from the timer input so that it can still be used as
general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input
capture function to be enabled.
• Signal priority:
20 TSSOP: SCK0 > IOC3 > GPO
32 LQFP: SCK0 > IOC5 > GPO
Others: SCK0 > GPO
• The SPI0 MOSI signal is mapped to this pin when used with the SPI function. Depending on the
configuration of the enabled SPI0 the I/O state is forced to be input or output.
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. If the
TIM output compare signal is enabled and routed here the I/O state will be forced to output.
• 32 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. If the TIM
output compare signal is enabled and routed here the I/O state will be forced to output.
• Signal priority:
20 TSSOP: MOSI0 > IOC2 > GPO
32 LQFP: MOSI0 > IOC4 > GPO
Others: MOSI0 > GPO
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
175