MC9S12GRMV1 Datasheet, PDF (410/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-27. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
1
Oscillator monitor
fail pending
0
COP
time out
pending
0
1
1
X
1
0
1
0
X
X
Vector Fetch
POR
LVR
Illegal Address Reset
External pin RESET
Clock Monitor Reset
COP Reset
POR
LVR
Illegal Address Reset
External pin RESET
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f_VCORST.
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 10-34. RESET Timing
RESET
PLLCLK
S12_CPMU drives
S12_CPMU releases
RESET pin low
RESET pin
f_VCORST f_VCORST
)
)
)
(
(
(
512 cycles
256 cycles
possibly
RESET
driven low
externally
10.5.2.1 Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f_CMFA (see device electrical characteristics for values), the S12CPMU
MC9S12G Family Reference Manual, Rev.1.23
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