MC9S12GRMV1 Datasheet, PDF (350/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
On simultaneous matches the lowest channel number has priority so with this configuration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a
simultaneous match2/match1transitions to state2.
8.5.9 Scenario 8
Trigger when a routine/event at M2 follows either M1 or M0.
Figure 8-37. Scenario 8a
SCR1=0111
SCR2=0101
State1
M01 _State2
M2
Final State
Trigger when an event M2 is followed by either event M0 or event M1
Figure 8-38. Scenario 8b
SCR1=0010
SCR2=0111
State1
M2
State2
M01 _{Final State}
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
8.5.10 Scenario 9
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed
again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing
the SCR2 encoding as shown in red this scenario becomes possible.
Figure 8-39. Scenario 9
SCR1=0111
SCR2=1111
State1
M01 _State2
M01
M2
Final State
8.5.11 Scenario 10
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1.
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one
or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger
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