MC9S12GRMV1 Datasheet, PDF (219/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-44. PPSS Register Field Descriptions
Field
7-0
PPSS
Description
Port S pull device select—Configure pull device polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
1 Pulldown device selected
0 Pullup device selected
2.4.3.25 Port S Wired-Or Mode Register (WOMS)
Address 0x024E
R
W
Reset
7
WOMS7
0
1 _{Read: Anytime}
Write: Anytime
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
0
0
0
0
0
Figure 2-26. Port S Wired-Or Mode Register (WOMS)
Access: User read/write¹
1
0
WOMS1
WOMS0
0
0
Table 2-45. WOMS Register Field Descriptions
Field
Description
7-0
WOMS
Port S wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven
active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit
has no influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
2.4.3.26
Pin Routing Register 0 (PRR0)
NOTE
Routing takes only effect if PKGCR is set to select the 20 TSSOP package.
Address 0x024F
R
W
Reset
7
PRR0P3
0
1 _{Read: Anytime}
Write: Anytime
6
PRR0P2
5
4
3
2
PRR0T31 PRR0T30 PRR0T21 PRR0T20
0
0
0
0
0
Figure 2-27. Pin Routing Register (PRR0)
Access: User read/write¹
1
0
PRR0S1
PRR0S0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
221