MC9S12GRMV1 Datasheet, PDF (898/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

48 KByte Flash Module (S12FTMRG48K1V1)
26.3.2.9.1 P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 26-21 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 26-21. P-Flash Protection Scenario Transitions
From
To Protection Scenario¹
Protection
Scenario
0
1
2
3
4
5
6
7
0
X
X
X
X
1
X
X
2
X
X
3
X
4
X
X
5
X
X
X
X
6
X
X
X
X
7
X
X
X
X
X
X
X
X
1 _{Allowed transitions marked with X, see Figure 26-14 for a definition of the scenarios.}
26.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
Offset Module Base + 0x0009
7
6
R
0
DPOPEN
W
Reset
F¹
0
5
4
3
2
1
0
DPS[5:0]
F¹
F¹
F¹
F¹
F¹
F¹
= Unimplemented or Reserved
Figure 26-15. EEPROM Protection Register (EEPROT)
1 _{Loaded from IFR Flash configuration field, during reset sequence.}
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor