MC9S12GRMV1 Datasheet, PDF (513/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Analog-to-Digital Converter (ADC12B12CV2)
14.3.2.10 ATD Input Enable Register (ATDDIEN)
Module Base + 0x000C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R1
1
1
1
W
IEN[11:0]
Reset 1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-12. ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Table 14-19. ATDDIEN Field Descriptions
Field
Description
11–0
IEN[11:0]
ATD Digital Input Enable on channel x (x= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input
buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
14.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
W
CMPHT[11:0]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-13. ATD Compare Higher Than Register (ATDCMPHT)
Table 14-20. ATDCMPHT Field Descriptions
Field
Description
11–0
Compare Operation Higher Than Enable for conversion number n (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of
CMPHT[11:0] a Sequence (n conversion number, NOT channel number!) — This bit selects the operator for comparison
of conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
515